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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a f amily of 4-Mbit static RAMs organized as 524,288-words by 8-bit, f abricated by Mitsubishi's highperf ormance 0.25m CMOS technology . The M5M5408B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP. Two ty pes of TSOPs are av ailable, M5M5408BTP (normal-lead-bend TSOP) , M5M5408BRT (rev erse-lead-bend TSOP). These two ty pes TSOPs are suitable f or a surf ace mounting on double-sided printed circuit boards. From the point of operating temperature, the f amily is div ided into two v ersions; "Standard" and "I-v ersion". Those are * * * * * * * * * * *
FEATURES
Single +5V power supply Small stand-by current: 0.4A(3V,ty p.) No clocks, No ref resh Data retention supply v oltage=2.0V to 5.5V All inputs and outputs are TTL compatible. Easy memory expansion by S# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.25m CMOS Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
PART NAME TABLE
Version, Operating temperature Part name (## stands f or "FP","TP",and "RT") M5M5408B## -55H M5M5408B## -70H M5M5408B## -55HI M5M5408B## -70HI
Power Supply
5.0V 5.0V
Access time
Stand-by c urrent Icc(PD), Vcc=3.0V ty pical * 25C 0.4A 0.4A 25C 1A 1A Limit s (max.) 70C 15A 15A 85C --30A
max.
55ns 70ns 55ns 70ns
Activ e current Icc1 (5.0V, ty p.*) 50mA (10MHz) 25mA (1MHz)
Standard 0 ~ +70C I-v ersion -40 ~ +85C
*Ty pical v alues are sampled, and are not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A17 W# A13 A8 A9 A11 OE# A10 S# DQ8 DQ7 DQ6 DQ5 DQ4
VCC A15 A17 W# A13 A8 A9 A11 OE# A10 S# DQ8 DQ7 DQ6 DQ5 DQ4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND
Pin A0 ~ A18 S# ( S ) W# ( W ) OE# (OE) Vcc GND
Function Address input Chip select input Write control input Output inable input Power supply Ground supply
DQ1 ~ DQ8 Data input / output
Outline 32P2M-A (FP) 32P3Y-H (TP)
Outline
32P3Y-J (RT)
1
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT is organized as 524,288-words by 8-bit. These dev ices operate on a single +5.0V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. A write operation is executed during the S# low and W# low ov erlap time. The address(A0~A18) must be set up bef ore the write cy c le A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while S# are in an activ e state (S#=L). When setting S# at a high lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips. Setting the OE# at a high lev el,the output stage is in a highimpedance state, and the data bus contention problem in the write cy c le is eliminated. The power supply c urrent is reduced as low as 0.4A (25C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. Pin Mode Non selection Write Read DQ High-impedance Data input (D) Data output (Q) Icc Standby Activ e Activ e Activ e A0 ~ A18 S# ( S ) W# ( W ) OE# (OE) Vcc GND Function Address input Chip select input Write control input Output inable input Power supply Ground supply
FUNCTION TABLE
S# H L L L W# X L H H OE# X X L H
DQ1 ~ DQ8 Data input / output
High-impedance Read note: "H" and "L" in this table mean VIH and VIL, respectiv ely . "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A4 A5 A6 A7 A12 A14 A16 A17 A18 A15 A10 A11 A9 A8 A13
8 7 6 5 4 3 2 30 1 31 13 14 15
MEMORY ARRAY 524288 WORDS x 8 BITS
17 18 19 20 21
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
23 25 26 27 28 29 22 24
CLOCK GENERATOR
W# S# OE# VCC
(5V)
A0 A1 A2 A3
12 11 10 9
32
16
GND
(0V)
2
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C Standard I-v ersion Ratings Units
Vcc VI VO Pd Ta T stg
-0.3* ~ +7 -0.3* ~ Vcc + 0.3 0 ~ Vcc 700 0 ~ +70 -40 ~ +85 -65 ~ +150
V mW
C C
* -3.0V in case of AC (Pulse width _ 30ns) <
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter High-lev el input v oltage Low-lev el input v oltage
High-level output voltage 2
( Vcc= 5V 10%, unless otherwise noted)
Limits Conditions Min Ty p. Max Vcc+0.3V Units
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2 Icc3 Icc4
IOH= -1mA IOH= -0.1mA Low-lev el output v oltage IOL=2mA VI =0 ~ Vcc Input leakage current
High-level output voltage 1
2.2 -0.3 * 2.4
Vcc-0.5V
0.8 V 0.4 1 1
A
Output leakage current Activ e supply c urrent (CMOS-lev el input)
S# = VIH or OE# =VIH, VI/O = 0 ~ Vcc S# _ 0.2V, output-open < _ Other inputs < 0.2V or _ Vcc-0.2V > f =10MHz f =1MHz f =10MHz f =1MHz Standard I-v ersion
Activ e supply c urrent S# =VIL, output-open Other inputs= VIH or VIL (TTL-lev el input) Stand by s upply current Vcc =5.5V, max. (CMOS-lev el input) _ S# > Vcc-0.2V,other inputs=0~Vcc Stand by s upply current (TTL-lev el input) S# =VIH, other inputs= 0 ~ Vcc
-
50 25 60 30 1.0 1.0 -
80 30 90 40 30 60 3
mA
A mA
Note 1: Direction f or current f lowing into IC is indicated as positiv e (no mark). Note 2: Ty pical v alues are sampled at Vcc=5.0V and Ta=25C, and are not 100% tested.
_ * -3.0V in case of AC (Pulse width <30ns)
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions
(Vcc=5.0V10%, unless otherwise noted)
Limits Min Ty p. Max Units
CI CO
VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz
8 10 pF
3
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply v oltage Input pulse Input rise time and f all time Ref erence lev el 5.0V
(Vcc=5.0V10%, unless otherwise noted)
VIH=2.4V,VIL=0.6V (-70H, -70HI) VIH=3.0V,VIL=0V (-55H, -55HI ) 5ns VOH=VOL=1.5V Transition is measured 500mV f rom steady state voltage f or ten and tdis. Fig.1, CL=100pF (-70H, -70HI) CL=30pF (-55H, -55HI ) CL=5pF (f or ten,t dis)
1.8k DQ CL 990
Output loads
CL Includes scope and jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits Symbol Parameter Read cy cle time Address access time Chip select access time Output enable access time Output disable time af t er S# high Output disable time af t er OE# high Output enable time af ter S# low Output enable time af ter OE# low Data v alid time after address -55H, -55HI Min Max -70H, -70HI Min Max Units
tCR ta(A) ta(S) ta(OE) tdis (S) tdis (OE) ten(S) ten(OE) tV(A)
55 55 55 25 20 20 10 5 10
70 70 70 35 25 25 10 5 10
ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Limits Symbol Parameter Write cy cle time Write pulse width Address set up time
Address set up time with respect to W# high
-55H, -55HI Min Max
-70H, -70HI Min Max
Units
tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten(W) ten(OE)
55 40 0 50 50 25 0 0 20 20 5 5
70 50 0 60 60 30 0 0 25 25 5 5
Chip select set up time Data set up time Data hold time Write recov ery time Output disable time af t er W# low Output disable time af t er OE# high Output enable time af ter W# high Output enable time af ter OE# low
ns ns ns ns ns ns ns ns ns ns ns ns
4
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~18 ta(A) ta(S)
(Note3)
tCR
tv (A)
S#
tdis (S) ta (OE)
(Note3)
OE#
(Note3) W# = "H" lev el
ten (OE) ten (S) tdis (OE)
(Note3)
DQ1~8
VALID DATA
Write cycle ( W# control mode )
tCW A0~18
tsu (S) S#
(Note3) (Note4)
tsu (A-WH)
(Note3)
OE# tsu (A) W# tw (W) trec (W)
(Note4)
tdis (W) tdis(OE) DQ1~8
(Note 6) DATA IN STABLE
ten(OE) ten (W)
tsu (D)
th (D)
5
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S# control mode)
tCW A0~18 tsu (A) S# tsu (S) trec (W)
(Note4)
(Note5)
W#
(Note3)
(Note4) (Note3)
tsu (D) DQ1~8
(Note 6) DATA IN STABLE
th (D)
Note Note Note Note
3: Hatching indicates the state is "don't care". 4: A Write occurs during the ov erlap of a low S# and a low W#. 5: If W goes low simultaneously with or prior to S#, the output remains in the high impedance state. 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Vcc
(PD)
Parameter Power down supply v oltage Chip select input S#
Limits Test conditions Min Ty pical Max
Units
2
_ Vcc(PD) > 2.2V _ _ 2.2V > Vcc(PD) > 2.0V I-version Vcc=3.0V, Standard, S# _ Vcc-0.2V, > I-version Other input Standard =0 ~ Vcc I-version 85C 70C 40C 0~ 25C -40~ 25C
VI (S#)
Icc
(PD)
Power down supply c urrent
2.2 -
Vcc(PD)
30 15 3 1 1 A
V
1* 0.4* 0.4*
*Ty pical v alues are sampled, and are not 100% tested.
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recov ery t ime Limits Test conditions Min 0 5 Ty p Max Units ns ms
tsu (PD) trec (PD)
(3) TIMING DIAGRAM
S# control mode Vcc tsu (PD) 2.2V S#
_ S# > Vcc - 0.2V
4.5V
4.5V
trec (PD) 2.2V
7
revision-2.0e, Feb.12, 2002
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Revision History Revision No. K0.1e K0.2e History The first edition 1) Icc3 limit revised 2) Icc(PD) limit revised 3) Icc1,Icc2 conditions revised 1) Vcc Level in the Block Diagram rev ised 2) Icc3 limit (typ) revised The first product version Product lineup revised 1) Product lineup revised 2) Symbol notations revised: S -> S#, W-> W#, OE -> OE# 3) Icc(PD) conditions revised Date Jul.30, '98 Jun. 3, '99 Preliminary Preliminary
K0.3e
Jun.28, '99 Preliminary
K1.0e K1.1e 2.0e
Oct.12, '99 Oct.21, '99 Feb.12, '02
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8
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